Integrated circuits commonly include multiple timing signals that must operate in conjunction with one another to ensure that the integrated circuit operates properly. An example of such timing signals is set forth in commonly-owned, copending U.S. patent application Ser. No. 423,822, entitled SYNCHRONOUS SRAM HAVING ASYNCHRONOUS TEST MODE, incorporated by reference herein.
To optimize the performance of the internal timing of an integrated circuit, it is known to provide a number of interconnection schemes (often called "metallization options"), wherein each scheme provides a different timing variation for the circuit. Such interconnection schemes can be time intensive and expensive to implement, requiring a new circuit fabrication mask. In addition, according to such an approach, once the integrated circuit is packaged, no further timing adjustments can take place.
It is also known to alter the internal timing of an integrated circuit by providing a number of laser fusible links. By opening the links, delays are introduced into the internal timing of the device. Such timing alteration schemes are irreversible, however, and typically leave no room for testing other delay variations. In addition, like the alternate metallization schemes described above, once the integrated circuit is packaged, no further timing adjustments can take place.
U.S. Pat. No. 5,351,211 issued to Higeta et al. on Sep. 27, 1994, discloses a semiconductor integrated circuit having an internal delay element that is used for determining the timing parameters of a RAM and/or logic portion of the circuit. The circuit includes input and output latching circuits that are controlled by a clock signal. The clock signal that is used to activate the input latching circuit is delayed by an internal delay element, and the delayed clock signal is then used to activate an output latching circuit. The delay element can also be switched into a ring oscillator-type circuit. When optimal latching operation is achieved (indicating a certain inherent delay in the RAM and/or logic circuit), the oscillation frequency of the ring oscillator is used as a measure of the inherent delay. The delay element of Higeta et al. is programmable. By providing an input signal, TST, a variety of delay times for the delay element can be achieved. While Higeta et al. provides a method of measuring the overall speed of a RAM and/or logic circuit, there are no teachings on altering the actual internal timing signals of the circuit under test. In addition, the delay element illustrated in Higeta et al. requires a large number of inputs, requiring the circuit to include a serial input circuit or a large number of external inputs.
U.S. Pat. No. 5,389,828 issued to Shusei Tago on Feb. 14, 1995, discloses a programmable pulse delay generator for precisely adjusting the width of a pulse. The Tago patent utilizes a digital-to-analog converter that require a large number digital input signals and circuit elements.
U.S. Pat. No. 5,124,589 issued to Shiomi et al. on Jun. 23, 1992, discloses a self-timed random access memory (RAM) having clocked input and output data retain circuits that can be disabled (i.e., made functionally transparent) by the application of a voltage greater than an external clock voltage (a "super voltage"). Shiomi et al. has no teachings on altering the timing internal to the RAM.
U.S. Pat. No. 5,212,442 issued to O'Toole et al. on May 18, 1993, discloses a method and apparatus for altering the substrate biasing of a packaged integrated circuit. One embodiment illustrates a super voltage detect circuit coupled to a bond pad of the device that is used to adjust the substrate bias.
It would be desirable to provide an integrated circuit wherein multiple internal timing signals could be varied by an external signal after the integrated circuit is packaged. It would further be desirable to provide an integrated circuit wherein the internal timing signals could be adjusted without requiring a large number of input signals.